1. Field of the Invention
This invention relates to a Bi-CMOS semiconductor device having bipolar transistors and complementary MOS transistors formed on the same semiconductor substrate, and more particularly to a Bi-CMOS semiconductor device suitable for constituting a semiconductor memory device.
2. Description of the Related Art
Generally, in a Bi-CMOS semiconductor device, P-type wells and N-type wells are formed in a P-type semiconductor substrate, for example. In this case, N-channel MOS transistors are formed in the P-type well and P-channel MOS transistors are formed in the N-type well. Further, NPN bipolar transistors are formed in the N-type well.
In a case where an SRAM is constructed using the above Bi-CMOS semiconductor device, memory cells are generally formed of N-channel MOS transistors. In this case, since the N-channel MOS transistors are formed in the P-type well of the same conductivity type as the substrate (P), the N-channel MOS transistors are electrically connected to the P-type semiconductor substrate. For this reason, electrons in the P-type semiconductor substrate may tend to flow into the memory cells constructed by the N-channel MOS transistors. This may degrade the soft error-resistance of the memory cells.
Further, the potential of all the P-type wells is the same as that of the P-type substrate. Therefore, the potential of the P-type substrate is applied as the substrate bias voltage to the N-channel MOS transistors constituting the memory cells, as well as the other N-channel MOS transistors. As a result, it becomes impossible to apply different substrate bias voltages to the N-channel MOS transistors used as the memory cells and the other N-channel MOS transistors.
In general, the threshold voltage of the N-channel MOS transistors constituting the memory cells is preferably set to be slightly higher than that of the other N-channel MOS transistors in order to attain a good data holding characteristic. However, as described before, since the common substrate bias voltage is applied to all the N-channel MOS transistors in the conventional Bi-CMOS semiconductor device, the threshold voltage of the N-channel MOS transistors constituting the memory cells cannot be set higher than that of the other N-channel MOS transistors, making it impossible to attain a good data holding characteristic.